As the technology for manufacturing integrated circuits advances, more and more logic functions may be included in a single integrated circuit device. Modern integrated circuit (IC) devices include over 100,000 gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions, such as, for example, those in a general-purpose microprocessor. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires verification of the design of the circuit and also various types of electrical testing after manufacture.
Development of a test program for an IC and debugging of that program can be very time consuming and costly unless designers consider test issues during the logic design phase. Due to the increased complexity of VLSI chips, it is generally not feasible for test engineering to independently develop and debug test programs. The responsibility now lies with logic designers to design logic such that it is easy to test and such that it requires a reduced set of so-called test "vectors" to thoroughly test the design.
However, as the complexity of the circuit increases, so does the cost and difficulty of verifying and electrically testing each of the devices in the circuit. From an electrical test standpoint, in order to totally verify that each gate in a VLSI circuit functions properly, one must ideally be able to exercise each of the gates not only individually (in the digital sense, determining that it is neither stuck-open nor stuck-closed), but also in conjunction with the other gates in the circuit in all possible combinations of operations. This is normally accomplished by automated testing equipment (ATE) that employs test vectors to perform the desired tests. A test vector describes the desired test input (or signals), associated clock pulse (or pulses), and expected test output (or signals) for every package pin during a period of time, often in an attempt to "test" a particular gate (or macro). For complex circuitry, this may involve a large number of test vectors and accordingly a long test time. Macro and cell are used herein to mean the same thing and may be used interchangeably.
In addition, specific circuit configurations in the VLSI circuit may have some of its gates inaccessible for all but a special combination of signals, thereby hiding a fault unless a very specific pattern of signals is presented. However, the cost of performing such testing on 100% of the manufactured circuits is staggering, considering the high cost of the test equipment required to exercise each circuit in conjunction with the long time required to present each possible combination to each gate. This has in the past forced integrated circuit manufacturers to test less than all of the active devices in a chip, with the attendant quality levels of the product being less than optimal. Thus, one of the major problems in integrated circuit design is the ability to adequately test the final IC design, and this problem increases with increasing complexity of the integrated circuit.
One way to address this problem is through design for test (DFT). The key concepts in DFT are controllability and observability. Controllability is the ability to set and reset the state of every node in the circuit, while observability is the ability to observe either directly or indirectly the state of any node in the circuit. The purpose of DFT is to increase the ability to control and observe internal and external nodes from external inputs/outputs. That is, DFT techniques may be employed for logic verification and DC parametric tests.
Designing testability into any circuit will affect the circuitry to some degree. Additional logic will probably have to be added. This additional logic will increase the amount of silicon required to implement the design. The savings from enhanced testability do not usually show up until the development time and testing costs of the circuit and its end system are analyzed.
Circuit designers have used stuck-fault modeling techniques in improving the efficiency of the testing of such VLSI circuits. Stuck-fault modeling is directed not to stuck-open or stuck-closed defects in individual gates, but to the effect of such defective gates (and defective interconnections) resulting in stuck-high and stuck-low nodes of the logic circuit. Minimum patterns of test vectors are then derived for the exercising of the logic circuit. Applying such test vectors to the circuit detects stuck-high and stuck-low nodes if defects are present. Such techniques have been successful in improving the test efficiency of current generation VLSI circuits.
In conjunction with the stuck-fault modeling and associated test generation, other circuitry may be included in the VLSI circuit specifically designed to improving its testability. One type of test circuitry is a scan path in the logic circuit. A scan path consists of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. These latches can be loaded with a serial data stream ("scan in") presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation (at each of the nodes having a scan latch) stored in its respective latch. By serially unloading the contents of the latches ("scan out"), the result of the particular test operation at the associated nodes is read out and may be analyzed for improper node operation. Repetition of this operation with a number of different data patterns effectively tests all necessary combinations of the logic circuit, but with a reduced test time and cost compared to separately testing each active component or cell and all their possible interactions. Scan paths permit circuit initialization by directly writing to the latches (or registers) and directly observing the contents of the latches (or registers). Using scan paths helps to reduce the quantity of test vectors compared to traditional "functional mode" approaches. Techniques for scanning such data are discussed by E. J. McCluskey in "A Survey of Design for Testability Scan Techniques", VLSI Design (Vol. 5, No. 12, pp. 38-61, December 1984).
Also as VLSI technology is advancing, users of integrated circuits are desiring specially designed and constructed integrated circuits, for performing functions customized for the user's application. Such integrated circuits have been called Application-Specific Integrated Circuits (ASICs). For an ASIC device to be cost-competitive with general purpose microcomputers which may have special functions implemented in programmable firmware, and cost-competitive with a board design made up of smaller scale integrated circuits, the design time of the ASIC circuit must be short and the ASIC circuit must be manufacturable and testable at low cost. Accordingly, it is useful for such circuits to be modular in design, with each of the modules performing a certain function, so that a new ASIC circuit may be constructed by combining previously-designed circuit modules. Such an approach can also be used for non-ASIC microcomputers and microprocessors. Regardless of the end product, the use of a modular approach allows the designer to use logic which has previously been verified, and proven manufacturable. However, if logic modules containing existing scan paths are placed into a new circuit application, new test patterns will generally be required for the new device, thereby lengthening the design/manufacture cycle time.
A modular approach to utilizing scan paths and other testability circuits has been used to provide thorough coverage of all possible faults in an efficient manner. However, this approach utilizes system buses to set up and operate the scan test, so that even though each module is tested independently, the test pattern designed for a given module depends upon the operation of other modules in the logic circuit for purposes of bus control and module selection. This results in the testability of a particular module depending upon the fault-free operation of other modules. In addition, the ATPG program which sets the conditions for test of a given module depends upon the position of the module relative to other modules, and upon the operating features of such other modules. While reduced test times and costs are thus achieved by such modularity, the use of system buses to load and unload the scan paths in the individual modules may not only affect the operation of the particular module, but is likely to also preclude "porting" of the test program for a given module from one logic circuit to another.
Recently, MegaModules have been used in the design of ASICs. (MegaModule is a trademark of Texas Instruments Incorporated.) Types of MegaModules.TM. include SRAMs, FIFOs, register files, RAMs, ROMs, universal asynchronous receiver-transmitters (UARTs), programmable logic arrays and other such logic circuits. MegaModules.TM. are usually defined as integrated circuit modules of at least 500 gates in complexity and having a complex ASIC macro function. These MegaModules.TM. may be predesigned and stored in an ASIC design library. The MegaModules.TM. can then be selected by the designer and placed within a certain area on the desired IC chip. This allows ASIC designers to integrate MegaModules.TM. into their logic as easily as simple macros.
Conventionally, these MegaModules.TM. are available as standard catalog devices and are designed without testability. In order to test the ASIC, a custom test program must be developed for that particular chip. Because a custom testing program has to be devised for each custom chip, the costs associated therewith are greater than desired.
More recently, peripheral cells have been provided for input and output during normal operation of the chip, and also for input and output of testing signals for a testing program. These peripheral cells are typically of input, output, and input/output types. Testing programs have been previously devised that use input cells for the input test terminals and output cells for the output test terminals. This has the disadvantage of restricting the number of test pins of any type to the number of available signal pins of the same type.
Another solution to this testing problem of an ASIC is the use of a so-called Parallel Module Test.TM. (PMT), which is often referred to as a "direct connect" scheme. (Parallel Module Test is a trademark of Texas Instruments Incorporated.) PMT is a direct connect scheme, because it connects external pins to a MegaModule.TM. bypassing all other logic, buffers, etc. It is primarily intended as a logic verification testability scheme and has recently been enhanced to address limited VIH/VIL and ICCQ testability schemes. However, even PMT may have problems since the logic states of the ASIC's circuitry may be disturbed as part of the test process during test selection and enabling.
Another solution is the test access port and boundary-scan architecture defined by the IEEE 1149.1 standard, a so-called JTAG test port. IEEE 1149.1 is primarily intended as a system test solution. The IEEE 1149.1 standard requires a minimum of four package pins to be dedicated to the test function. The IEEE 1149.1 standard requires boundary scan cells for each I/O buffer, which adds data delay to all normal operation function pins as well as silicon overhead. Although it has "hooks" for controlling some internal testability schemes, it is not optimized for chip-level testing. IEEE 1149.1 does not explicitly support testing of internal DC parametrics.
For a manufacturer, DC parametrics are just as important to the test process as is logic verification testing, which was described earlier herein. In general, DC parametric tests are employed to evaluate the quality of the fabrication of the individual gates and their interconnections, rather than testing their logical operation as the earlier described tests perform. A test engineer must evaluate the test patterns to find appropriate test vectors where the device is in a state suitable for the performance of DC parametric tests. In conventional logic tests, opportunities for conducting DC parametric tests are scattered throughout the test patterns. What is needed is a simpler, easier, and faster way to generate efficient test patterns useful to perform DC parametric tests.
Many testability schemes have been described that would increase testing quality and/or reduce test time. A partial list includes the disabling of DC through-current for pullup (PU) and pulldown (PD) cells, directing the output of a VIH/VIL tree to a non-dedicated package pin, forcing a high-impedance state for 3-state I/O buffers, and logic verification of MegaModules.TM. via Parallel Module Test.TM.. However, there is no common control method defined for all these testability schemes.
As a result silicon efficiency is poor, because the control circuit for each testability scheme has its own unique logic and package pin resource requirements. Design and test engineering efficiency is poor, because few of these testability schemes are well-defined and supported by standard testing software. Finally, new testability schemes cannot capitalize on existing silicon, engineering expertise, and software resources.
In addition, there is no common control technique for all of these various known testing schemes. That is, each test scheme has its own control technique. Even JTAG is unable to control all these test schemes without modification.
These and other disadvantages of the prior art are overcome by the present invention, however, and improved methods and apparatus for chip-level testing, as well as system-level testing, are provided.